/* * Author : Kavita Bala * Email : kaybee@lcs.mit.edu * Comment : Header file with all declarations for the STLB */ #define KB_DEBUG 0 /* Offsets for temporaries to store the k1, t0, t1, and AT registers */ #define KB_K1 32 /* 8 */ #define KB_T0 36 /* 9 */ #define KB_T1 40 /* 10 */ #define KB_AT 44 /* 11 */ /* Offsets for temporaries to store the status, epc, tlb_miss_next used for FIFO TLB management in lower partition */ #define KB_STATUS 48 /* 12 */ #define KB_EPC 52 /* 13 */ #define KB_TLB_MISS_NEXT 56 /* 14 */ #define KB_TLB_MISS_NEXT_PTR 14 /* Offset for counter of number of TLB misses serviced by the STLB, total TLB misses, number of system calls */ #define KB_STLB_SERVICED 60 /* 15 */ #define KB_STLB_SERVICED_PTR 15 #define KB_TOTAL_TRAPS 64 /* 16 */ #define KB_TOTAL_TRAPS_PTR 16 #define KB_TRAP_SYSCALL 92 /* 23 */ #define KB_TRAP_SYSCALL_PTR 23 /* Offset for temporaries to store k1, t1, and AT when getting counter readings */ #define KB_TMR_K1 96 /* 24 */ #define KB_TMR_T1 100 /* 25 */ #define KB_TMR_AT 104 /* 26 */ /* Various tempraries for timings, and counts */ #define KB_TMR_START_PTR 30 #define KB_TMR_START 30*4 #define KB_NESTED_PTR 31 #define KB_NESTED 31*4 #define KB_TLB_PENALTIES_PTR 32 #define KB_TLB_PENALTIES 32*4 #define KB_OTHER_PENALTIES_PTR 33 #define KB_OTHER_PENALTIES 33*4 #define KB_STLB_PENALTIES_PTR 34 #define KB_STLB_PENALTIES 34*4 #define KB_READING_IOC_COST 14 #define KB_UPPER_LIMIT 10000 /* Since the STLB has 4K entries the number of bits to be extracted as * an index are 12. We select 0x7ff8 so that the lower 3 bits are 0 for * alignment, and since each STLB entry consists of 8 bytes. */ #define KB_STLB_INDEX_CTXT_MASK 0x7ff8 /* * Since 12 bits are used for the index. 12 for the offset within a page. Out * of 32, 32-24 = 8 bits are used as a tag check */ #define KB_STLB_TAG_MASK 0xff #define KB_STLB_VALID_MASK 0x00000200 /* PG_V */ #define KB_STLB_DIRTY_MASK 0x00000400 /* TLB_LO_D */ #define KB_STLB_L2_MASK 0x00000100 /* PG_G */ /* * Manipulations of the faulting TLB address */ #define KB_STLB_SHIFT_VADDR 9 #define KB_STLB_TAG_SIZE 8 #define KB_L2_CHECK_SHIFT 31 /* * Size specifications */ #define KB_PAGE_SIZE 4*1024 /* in bytes */ #define KB_NO_OF_ENTRIES_PER_PAGE 1024 /* Since each entry is 4 bytes */ #define KB_STLB_NO_OF_ENTRIES 4*1024 /* no of entries in STLB*/ #define KB_STLB_BYTE_SIZE 8*KB_STLB_NO_OF_ENTRIES /* Since each entry occupies 8 bytes */ #define KB_TLB_LOAD_POINT 0x80000008 /* Where does a double miss take place */ /* kb Tue Aug 9 15:38:21 1994 * Timer */ #define KB_STLB_TMP_SPACE_SIZE KB_PAGE_SIZE /* Temporary space added for maintaining data structures */ #ifndef ASSEMBLER #define TW_RESET -2 #define TW_STATS -3 struct kb_stlb_stats { int tlb_traps; int l1k; int l2; int kpt; int user_pt; int prefetch_l1k; int prefetch_l2; int prefetch_kpt; int stlb_serviced; int ast; int syscall; int intr; }; /* * kb Tue Aug 9 15:34:46 1994 * Timer * Adding timer data structures to store a table of each interrupt time. */ struct kb_tmr_stats { int tlb_traps; int l1k; int l2; int kpt; int user_pt; int prefetch_l1k; int prefetch_l2; int prefetch_kpt; int stlb_serviced; int ast; int syscall; int intr; int l1k_inv; int l2_inv; int kpt_inv; int user_pt_inv; int other; int stlb_general_hit; int stlb_double_entry_hit; int stlb_l2_entry_hit; int stlb_fail; int l1k_time; int l2_time; int stlb_time; int other_time; int kpt_time; int user_pt_time; int l1k_inv_time; int l2_inv_time; int kpt_inv_time; int user_pt_inv_time; int stlb_general_hit_time; int stlb_double_entry_hit_time; int stlb_l2_entry_hit_time; int stlb_fail_time; int tmr_max; int tmr_min; }; #endif /* @(#)tmrreg.h 1.5 8/10/89 * Definitions for the PMAX timer board. * * Russell Nakano * 07/28/89 * */ /* kb * Tue Aug 9 15:28:12 1994 * Adding the IOASIC code to my locore.s to calculate the time for a * interrupt handler. */ #define IOC_CTR 0xbf8401e0 /* @(#)tmrreg.h 1.5 8/10/89 * Definitions for the PMAX timer board. * * Russell Nakano * 07/28/89 * */ /* kb * Tue Aug 9 15:28:12 1994 * Adding the IOASIC code to my locore.s to calculate the time for a * interrupt handler. */ #define IOC_CTR 0xbf8401e0 #ifndef ASSEMBLER #define IOC_RD (*(volatile unsigned int *)(IOC_CTR)) #else #define TSTAMP(tmp1_reg,tmp2_reg,tmp3_reg,tmp4_reg) \ li tmp1_reg, IOC_CTR; \ lw tmp1_reg,0(tmp1_reg); \ lw tmp2_reg, KB_TMR_COUNT(AT); \ addu tmp3_reg, AT, 4096; \ addu tmp3_reg, tmp2_reg; \ addu tmp2_reg, 4; \ or tmp4_reg, zero, 0x1; \ sll tmp4_reg,20; \ bne tmp2_reg, KB_AS_TMP_SIZE,1f; \ sw tmp1_reg, 0(tmp3_reg); \ move tmp2_reg, zero; \ 1: sw tmp2_reg, KB_TMR_COUNT(AT) #endif